1. Field of the Invention
The present invention relates to a method of forming a high voltage metal oxide semiconductor (HVMOS) transistor, and more particularly, to a method of forming a HVMOS transistor with a double diffuse drain (DDD).
2. Description of the Prior Art
Double diffuse drain (DDD) is a source/drain structure that is applied to HVMOS transistors. The DDD structure is able to provide the HVMOS transistor with a higher breakdown voltage. This can prevent a high voltage, such as electrostatic discharge (ESD), from damaging the transistor. Furthermore, the hot electron effect resulting from short channel is avoided.
Please refer to FIG. 1 showing a schematic diagram of a conventional HVMOS transistor 10 with DDD. As shown in FIG. 1, the HVMOS transistor 10 is formed in a substrate 12. The substrate 12 comprises two field oxide layers 14 formed in the substrate 12, a first conductive type well 16 formed in the substrate 12 between the field oxide layers 14, a gate 26 formed on the substrate 12 between the field oxide layers 14, and a gate oxide layer 24 between the gate 26 and the substrate 12. In addition, the substrate 12 comprises two second conductive type first doped regions 30 positioned in the substrate 12 between the gate 26 and the two field oxide layers 14, and two second conductive type second doped regions 32 positioned above the first doped regions 30.
Please refer to FIG. 2 to FIG. 5. FIG. 2 to FIG. 5 are schematic diagrams illustrating a method of forming the HVMOS transistor 10 according to the prior art. As shown in FIG. 2, first a substrate 12 is provided. Then, a thermal oxidation process is performed to form two field oxide layers 14 in the substrate 12, and a first conductive type well 16 is formed in the substrate 12. It is worth noting that if the desired HVMOS transistor 10 is N type, the first conductive type is P type, and if the desired HVMOS transistor 10 is P type, the first conductive type is N type.
As shown in FIG. 3, an oxide layer 18 and a polysilicon layer 20 are sequentially formed on the substrate 12, and a photoresist layer 22 is coated on the polysilicon layer 20. Then as shown in FIG. 4, an exposure process and a development process are performed to remove a portion of the photoresist layer 22 for forming a patterned photoresist layer (not shown). Then, an etching process is performed by utilizing the patterned photoresist layer (not shown) as a mask to remove the polysilicon layer 20 and the oxide layer 18 which are not covered by the mask such that a gate oxide layer 24 and a gate 26 are formed on the substrate 12. Finally, the patterned photoresist layer (not shown) is removed.
As shown in FIG. 5, another photoresist layer (not shown) is coated on the substrate 12, and an exposure process and a development process are sequentially performed to form a patterned photoresist layer 28 on the field oxide layers 14. Then, an ion implantation process is performed by utilizing the gate 26 and the patterned photoresist layer 28 as a hard mask to form two second conductive type first doped regions 30 in the substrate 12. Thereafter, another ion implantation process is performed to form two second conductive type second doped regions 32. It is worth noting that if the desired HVMOS transistor 10 is N type, the second conductive type is N type, and if the desired HVMOS transistor 10 is P type, the second conductive type is P type.
According to the prior art, the gate 26 and the patterned photoresist layer 28 above the two field oxide layers 14 are utilized as a hard mask, and two ion implantation processes are consecutively performed to form two first doped regions 30 and two second doped regions 32 which serve as the DDD of the HVMOS transistor 10. However, the thickness of the gate 26 hinders the doped energy during the ion implantation processes. Once the doped energy is too high, the doped ions will pass through the gate 26 and enter into the gate oxide layer 26 such that the gate 26 and the substrate 12 are short-circuited. Consequently, the first doped regions 30 and the second doped regions 32 cannot reach to an ideal depth according to the prior art due to the doped energy limitation. This makes the conventional HVMOS transistor 10 have a relatively poor breakdown voltage. Take a conventional N type HVMOS transistor for example. The breakdown voltage is about 20V, which does not meet the high voltage requirement (20V to 30V) for HVMOS transistors.